Electron Transport in Si Nanowires

We investigate electron transport in silicon nanowires taking into account acoustic, non-polar optical phonons and surface/interface roughness scattering. We find that at very high transverse fields the reduced density of final states to which the carriers can scatter into gives rise to a reduced influence of interface-roughness scattering, which is promising result from a fabrication point of view. 1. Motivation and Model Description Nanowires (NW) and nanotubes are expected to exhibit one-dimensional (1D) transport and hence improved mobility due to the reduced density of states for scattering [1] and reduced number of propagating modes. The enhancement of phonon limited mobility due to subband modulation in ultrathin SOI MOSFETs has also been reported [2]. Although there have been claims of high electron mobility in silicon nanowires [3,4], recent paper [5] contradicts these results. Kotlyar, et al., investigated the phonon limited mobility in a cylindrical SiNW and found it to be no better than the one in two-dimensional (2D) MOSFETs. The objective of this paper is to investigate the mobility of electrons in a rectangular SiNW, by taking into account the major scattering mechanisms such as acoustic phonon, non-polar optical phonon, and surface roughness scattering. The effect of surface roughness is considered using two different models. The phonons are treated in bulk mode approximation. The effect of the phonon confinement is not taken into consideration in calculating the scattering rates. The modification of the phonon spectrum due to spatial confinement [6] is expected to enhance the overlap of the electron and confined phonon wave function, thus increasing the electronphonon scattering. This increase is not expected to be significant [5] for the dimensions considered in this work. The paper is organized as follows: Section 2 describes the various components of the simulator used in the mobility calculation. The device structures used in this study and the corresponding simulation results are presented in Section 3. We finish this work (Section 4) with some conclusive remarks regarding the research done and directions for future research. 2. Simulator Components Description The device considered for this research work is described in more details in Ref. [7]. Briefly, the SOI device structure consists of a 100 nm silicon substrate, on top of which is grown 80 nm of buried oxide. The thickness of the SOI layer is 8 nm and the width is 30 nm (varies to 8 nm). On top of the SOI layer sits the gate-oxide layer with thickness of 25 nm. This device has been used to compare the mobility data obtained by Takagi et al. [7] for a 2-d electron gas. The doping in the channel is 3×10 cm. Institute of Physics Publishing Journal of Physics: Conference Series 38 (2006) 126–129 doi:10.1088/1742-6596/38/1/031 NPMS-7/SIMD-5 (Maui 2005) 126 © 2006 IOP Publishing Ltd Report Documentation Page Form Approved OMB No. 0704-0188 Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. 1. REPORT DATE 2006 2. REPORT TYPE N/A 3. DATES COVERED 4. TITLE AND SUBTITLE Electron Transport in Si Nanowires 5a. CONTRACT NUMBER